The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly to a method for manufacturing a capacitor of a semiconductor device utilizing the microscopic structure of a polycrystalline silicon.
A stacked capacitor cell which uses a silicon nitride layer as a dielectric film and a polycrystalline silicon layer as an electrode has been widely adopted in DRAM cells. However, along with the trend toward high packing density in DRAMs, sufficient cell capacitance is difficult to obtain using such conventional stacked capacitor cells. Thus, methods for enlarging the effective area of a capacitor are sought, such as changing the structure of the stacked capacitor. Other methods change the capacitor material, such as using a tantalum oxide layer having a high dielectric constant in place of silicon nitride as the dielectric film.
In one method for enlarging the capacitor's effective area, the polycrystalline silicon layer utilized as a storage electrode of the capacitor is formed so that its surface is rugged. This ruggedness can be attained by etching the surface of the polycrystalline silicon layer, or by controlling the growing conditions of the polycrystalline silicon layer. Controlling the growing conditions is usually preferred, because it can be implemented using relatively simple processing techniques.
FIGS. 1-5 illustrate conventional methods for controlling the growing conditions of a polycrystalline silicon layer to create a rugged surface thereof.
A method for making the surface of a polycrystalline silicon layer rugged by controlling the growing conditions thereof suggested by Yoshimura et al. will be first explained ("Rugged Surface Poly-Si Electrode and Low Temperature Deposited Si.sub.3 N.sub.4 for 64 Mbit and beyond STC DRAM Cell" by M. Yoshimura et al., IEDM 1990, pp. 659-662). Here, FIGS. 1 and 2 are photographs which illustrate the method for manufacturing a capacitor of a semiconductor device by the Yoshimura method. More particularly, FIG. 1 shows the variation in surface morphology (degree of ruggedness) of a polycrystalline silicon layer according to its deposition temperature for a given deposition thickness (0.1 .mu.m). Also, FIG. 2 shows the variation in surface morphology (degree of ruggedness) of a polycrystalline silicon layer according to its deposition thickness for a given deposition temperature (570.degree. C.).
From the teaching of Yoshimura et al., it is noted that the degree to which the surface is rugged varies depending upon the deposition temperature (refer to FIG. 1) and deposition thickness (refer to FIG. 2). That is, Yoshimura et al. teach that the surface is most markedly rugged when the polycrystalline silicon layer is deposited to a thickness of 0.1 .mu.m at a temperature of about 570.degree. C. Given a constant capacitor size and structure, the effective cell capacitor area obtained from the use of the rugged polycrystalline silicon layer introduced in the above paper is approximately 2.5 times that obtained by way of a polycrystalline silicon layer having a comparatively smooth surface.
FIGS. 3 through 5 are sectional views showing another conventional method for manufacturing the capacitor of a semiconductor device suggested by M. Sakao et al. ("A Capacitor-Over-Bit-line (COB) Cell with a Hemispherical-Grain Storage Node for 64 Mb DRAMs" by M. Sakao et al., IEDM 1990, pp. 655-658).
After forming a central storage electrode 20 on a semiconductor substrate 10 (FIG. 3), a polycrystalline silicon layer 30 having hemispherical grains is deposited on the surface of the structure (FIG. 4). Anisotropic etching is carried out on the surface of the resultant structure, so that the shape of the hemispherical-grain is transferred to the central storage electrode 20, completing storage electrodes 20a and 30a having rugged surfaces (FIG. 5).
Polycrystalline silicon layer 30 which is deposited on the resultant structure having the central storage electrode thereon is obtained when 20% He-diluted silane (SiH.sub.4) is deposited on the semiconductor substrate, in a specific condition of 1.0 tort and at 550.degree. C. This is similar to the method of the paper cited with reference to FIGS. 1 and 2 in that the surface of the polycrystalline silicon layer is also made rugged by controlling the growing conditions of the polycrystalline silicon layer.
FIGS. 6 through 8 are views for illustrating still another conventional method for manufacturing a semiconductor device suggested by Pierre C. Fazan and Akram Ditali ("Electrical Characterization of Textured Interpoly Capacitors for Advanced Stacked DRAMs" by Pierre C. Fazan and Akram Ditali, IEDM 1990, pp. 663-666).
After depositing a polycrystalline silicon layer 50 to a thickness of about 200-300 nm on a semiconductor substrate 10, implantation of phosphorus ions takes place (FIG. 6). At this time, the phosphorus ions are, for the most part, doped on the boundary portions of the grains constituting the polycrystalline silicon layer. This is because the bonding force between the silicon ions in those portions is weaker than that in other portions. Successively, the surface portion of the resultant structure is subjected to a wet oxidization at a temperature of about 907.degree. C. Here, since the water molecules (H.sub.2 O) supplied during the wet oxidation react with the silicon atoms constituting the polycrystalline silicon layer in the boundary portions greater than the other portion, a greater than average amount of silicon dioxide (SiO.sub.2) 60 is generated thereby forming a rugged polycrystalline silicon layer 50a (FIG. 7). If the resultant structure with the silicon dioxide is wet etched, grooves occur in the portions (i.e., the boundary portions of the grains) with greater silicon dioxide, so that the rugged and uneven polycrystalline silicon layer 50a is obtained (FIG. 8).
According to the above methods, the surface of the polycrystalline silicon layer is made rugged, taking advantage of the weak bonding force in the boundary portions of the grains constituting the polycrystalline silicon layer. Compared with the effective area of an ordinary polycrystalline silicon layer (whose surface is not rugged), the methods for enlarging the effective area by making the surface of the polycrystalline silicon layer rugged greatly contribute to packing density of the DRAMs, since a two to three times larger effective area can be obtained. However, methods for obtaining the surface ruggedness by controlling the growing conditions of the polycrystalline silicon layer (FIGS. 1 & 2 and 3-5) have problems with respect to uniformity and reproducibility. Also, the method for making the surface rugged by directly etching the polycrystalline silicon layer according to Fazan et al. has problems in obtaining sufficient cell capacitance.